As is known, in modern microelectronics, reduction of the overall dimensions of devices is one of the main objectives. In particular, in the fabrication of memories of a non-volatile type, it is important to minimize the overall dimensions of each memory cell. The need to obtain an increasingly wider integration scale entails, however, certain difficulties. In some cases, for example, the alignment of the masks used in the different processing steps using traditional processes calls for a precision that, in practice, is frequently not possible to achieve. In particular, a major problem is to align the masks normally utilized, on the one hand, for defining the active areas accommodating the memory cells and, on the other, for shaping the polysilicon layer extending on top of the active areas and forming the floating gates of the cells.
So-called self-aligned processes have consequently been developed, and enable the more critical masking steps to be eliminated, exploiting the surface conformation of the wafer. For greater clarity, reference may be made to FIGS. 1 to 4, showing a semiconductor wafer 1 having a substrate 10, for example of monocrystalline silicon. The wafer 1 comprises conductive active areas 2, insulated by shallow-trench-insulation (STI) structures 3, or else, alternatively, by insulation structures formed through local oxidation of silicon (LOCOS). In practice, the insulation structures 3 comprise trenches of a preset depth, filled with silicon dioxide. In either case, the insulation structures 3 project from the surface 4 of the wafer 1, adjacent to the active areas 2; in this way, the insulation structures 3 define recesses 5 exactly on top of the active areas 2.
Channel regions of memory cells (not illustrated herein) are made inside the active areas 2 by implanting and diffusing dopant species and using thermal oxidation; then a thermal oxidation provides a gate oxide layer 7, of the thickness of a few nanometers. Subsequently, a conductive polysilicon layer 8 is deposited, as illustrated in FIG. 2.
The conductive layer 8 fills the recesses 5 and has a thickness such as to cover completely the projecting portions of the insulation structures 3.
Next (FIG. 3), a chemical-mechanical-polishing (CMP) planarization is performed, which is stopped when the insulation structures 3 are again exposed. In this way, the entire polysilicon layer 8 is removed, except for residual portions, which occupy the recesses 5 and are consequently perfectly aligned to the active areas 2. In practice, the residual portions of the polysilicon layer 8, which are insulated from the respective active areas 2 thanks to the oxide layer 7, form floating gates 11 of the memory cells.
The process further comprises forming an insulating layer 12, which coats the floating gates 11 of the polysilicon layer 8, and depositing a further polysilicon layer, which is in turn defined for forming control gates 13 of the memory cells.
The known self-aligned processes, although advantageous as regards the possibility of increasing the integration scale, present, however, other limitations. Traditional processes, in fact, enable passive components (normally resistors and capacitors) to be formed on top of the insulating structures. In particular, these components and floating gates of the memory cells may be formed starting from the same polysilicon layer using a single mask. This is particularly useful for forming parts of read/write circuits of the memory cells, which are normally integrated in the same wafer, but must withstand much higher voltages and currents. The gate oxide is in fact too thin for eliminating the inevitable capacitive coupling of the high-voltage passive elements with the substrate and is highly subject to breakdown if subjected to high voltages. In addition, traditional processes enable standard cells and high-performance cells to be formed in the same wafer. In particular, in the high-performance cells, the floating terminal is shaped so as to extend in part also outside of the active areas and is consequently better coupled to the control gate: these cells may consequently be driven more rapidly and/or with lower voltages.
It is, however, evident that known self-aligned processes do not enable either passive components or high-performance cells to be formed on top of the insulating structures. On the one hand, in fact, the CMP treatment removes completely the polysilicon overlying the insulating structures, where no conductive material is available to form electrical components; it is consequently necessary to depose and define a new polysilicon layer. On the other hand, precisely because the processes are self-aligned, the recesses where the floating gates of the cells are formed have the same dimensions as the underlying active areas and consequently it is not possible to improve the coupling.